1. Field of the Invention
The invention relates to an arrangement structure of cells, and more particularly to an arrangement structure of cells of a storage device.
2. Description of the Related Art
FIG. 1 is a schematic diagram of a conventional arrangement for cells. When the word line WL is asserted, the transistors in the cells C0˜C3 are turned on. Thus, the bit lines BL0˜BL3 are capable of tramsmitting a corresponding level. Referring to FIG. 1, when the transistors in the cells C0˜C3 are turned on, the bit line BL1 transmits a high level and the bit lines BL0, BL2, and BL3 transmit a low level (e.g. VSS).
However, coupling capacitances exist between the bit line BL1 and the neighboring bit line, such as BL0 and BL2. The bit line BL1 may transmits an abnormal level (e.g. low level) due to the coupling capacitances. To solve the problem, the conventional method utilizes pull-up loads to connect the bit lines. However, costs are increased. Furthermore, unnecessary current paths are formed due to the extra pull-up loads. Thus, power consumption is increased.